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[/] [pci/] [tags/] [rel_5/] [sim/] [rtl_sim/] [bin/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5584d 17h /pci/tags/rel_5/sim/rtl_sim/bin/
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7815d 03h /pci/tags/rel_5/sim/rtl_sim/bin/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7818d 09h /pci/tags/rel_5/sim/rtl_sim/bin/
62 Added BIST signals for RAMs. mihad 7929d 08h /pci/tags/rel_5/sim/rtl_sim/bin/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7937d 08h /pci/tags/rel_5/sim/rtl_sim/bin/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7937d 09h /pci/tags/rel_5/sim/rtl_sim/bin/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7979d 09h /pci/tags/rel_5/sim/rtl_sim/bin/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7985d 14h /pci/tags/rel_5/sim/rtl_sim/bin/
27 Modified testbench and fixed some bugs mihad 8160d 08h /pci/tags/rel_5/sim/rtl_sim/bin/
26 Modified testbench and fixed some bugs mihad 8160d 09h /pci/tags/rel_5/sim/rtl_sim/bin/
16 Import of various scripts for simulation running mihad 8178d 12h /pci/tags/rel_5/sim/rtl_sim/bin/

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