URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_5/] [sim/] [rtl_sim/] [run/] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5587d 02h	/pci/tags/rel_5/sim/rtl_sim/run/
82	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7817d 12h	/pci/tags/rel_5/sim/rtl_sim/run/
81	Updated synchronization in top level fifo modules.	mihad	7817d 12h	/pci/tags/rel_5/sim/rtl_sim/run/
73	Bug fixes, testcases added.	mihad	7826d 18h	/pci/tags/rel_5/sim/rtl_sim/run/
72	* empty log message *	mihad	7873d 22h	/pci/tags/rel_5/sim/rtl_sim/run/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 00h	/pci/tags/rel_5/sim/rtl_sim/run/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 17h	/pci/tags/rel_5/sim/rtl_sim/run/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7979d 01h	/pci/tags/rel_5/sim/rtl_sim/run/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7987d 23h	/pci/tags/rel_5/sim/rtl_sim/run/
42	Removed out of date files	mihad	8000d 00h	/pci/tags/rel_5/sim/rtl_sim/run/
26	Modified testbench and fixed some bugs	mihad	8162d 17h	/pci/tags/rel_5/sim/rtl_sim/run/
22	Added short description for simulation running	mihad	8180d 18h	/pci/tags/rel_5/sim/rtl_sim/run/
17	* empty log message *	mihad	8180d 20h	/pci/tags/rel_5/sim/rtl_sim/run/