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[/] [pci/] [tags/] [rel_6/] - Rev 69

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Rev Log message Author Age Path
69 Changed BIST signal names etc.. mihad 7914d 08h /pci/tags/rel_6/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7917d 17h /pci/tags/rel_6/
67 Changed BIST signals for RAMs. tadejm 7917d 22h /pci/tags/rel_6/
66 Changed empty status generation in pciw_fifo_control.v mihad 7921d 09h /pci/tags/rel_6/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7924d 07h /pci/tags/rel_6/
64 The testcase I just added in previous revision repaired mihad 7924d 09h /pci/tags/rel_6/
63 Added additional testcase and changed rst name in BIST to trst mihad 7924d 11h /pci/tags/rel_6/
62 Added BIST signals for RAMs. mihad 7927d 04h /pci/tags/rel_6/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7935d 04h /pci/tags/rel_6/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7935d 05h /pci/tags/rel_6/
58 Removed all logic from asynchronous reset network mihad 7940d 05h /pci/tags/rel_6/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7940d 11h /pci/tags/rel_6/
56 Number of state bits define was removed mihad 7941d 02h /pci/tags/rel_6/
55 Changed state machine encoding to true one-hot mihad 7941d 02h /pci/tags/rel_6/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7974d 04h /pci/tags/rel_6/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7974d 07h /pci/tags/rel_6/
52 Oops, never before noticed that OC header is missing mihad 7974d 12h /pci/tags/rel_6/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7974d 12h /pci/tags/rel_6/
50 Got rid of undef directives mihad 7977d 04h /pci/tags/rel_6/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7977d 04h /pci/tags/rel_6/

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