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[/] [pci/] [tags/] [rel_6/] - Rev 76

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Rev	Log message	Author	Age	Path
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7823d 18h	/pci/tags/rel_6/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7826d 19h	/pci/tags/rel_6/
73	Bug fixes, testcases added.	mihad	7826d 19h	/pci/tags/rel_6/
72	* empty log message *	mihad	7873d 23h	/pci/tags/rel_6/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7881d 15h	/pci/tags/rel_6/
69	Changed BIST signal names etc..	mihad	7918d 22h	/pci/tags/rel_6/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7922d 08h	/pci/tags/rel_6/
67	Changed BIST signals for RAMs.	tadejm	7922d 13h	/pci/tags/rel_6/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7925d 23h	/pci/tags/rel_6/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7928d 21h	/pci/tags/rel_6/
64	The testcase I just added in previous revision repaired	mihad	7928d 23h	/pci/tags/rel_6/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7929d 01h	/pci/tags/rel_6/
62	Added BIST signals for RAMs.	mihad	7931d 18h	/pci/tags/rel_6/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7939d 18h	/pci/tags/rel_6/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7939d 19h	/pci/tags/rel_6/
58	Removed all logic from asynchronous reset network	mihad	7944d 20h	/pci/tags/rel_6/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7945d 02h	/pci/tags/rel_6/
56	Number of state bits define was removed	mihad	7945d 16h	/pci/tags/rel_6/
55	Changed state machine encoding to true one-hot	mihad	7945d 17h	/pci/tags/rel_6/
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	7978d 19h	/pci/tags/rel_6/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] - Rev 76

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