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[/] [pci/] [tags/] [rel_6/] [apps/] [crt/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5555d 00h /pci/tags/rel_6/apps/crt/
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7589d 19h /pci/tags/rel_6/apps/crt/
96 Update! mihad 7652d 22h /pci/tags/rel_6/apps/crt/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7688d 20h /pci/tags/rel_6/apps/crt/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7688d 20h /pci/tags/rel_6/apps/crt/
84 Changed vendor ID. mihad 7746d 15h /pci/tags/rel_6/apps/crt/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7788d 16h /pci/tags/rel_6/apps/crt/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7791d 15h /pci/tags/rel_6/apps/crt/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7794d 16h /pci/tags/rel_6/apps/crt/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7907d 16h /pci/tags/rel_6/apps/crt/
31 User defined constants used for Test Application tadej 8127d 12h /pci/tags/rel_6/apps/crt/
29 Xilinx synthesys log file tadej 8127d 23h /pci/tags/rel_6/apps/crt/
25 *** empty log message *** mihad 8148d 14h /pci/tags/rel_6/apps/crt/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8148d 17h /pci/tags/rel_6/apps/crt/
14 *** empty log message *** mihad 8148d 19h /pci/tags/rel_6/apps/crt/
2 New project directory structure mihad 8270d 17h /pci/tags/rel_6/apps/crt/

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