URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [apps/] [crt/] [syn/] - Rev 154

Rev	Log message	Author	Age	Path
154	New directory structure.	root	5577d 23h	/pci/tags/rel_6/apps/crt/syn/
112	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7612d 18h	/pci/tags/rel_6/apps/crt/syn/
96	Update!	mihad	7675d 21h	/pci/tags/rel_6/apps/crt/syn/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7711d 18h	/pci/tags/rel_6/apps/crt/syn/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7711d 18h	/pci/tags/rel_6/apps/crt/syn/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7811d 14h	/pci/tags/rel_6/apps/crt/syn/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7814d 14h	/pci/tags/rel_6/apps/crt/syn/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7930d 15h	/pci/tags/rel_6/apps/crt/syn/
29	Xilinx synthesys log file	tadej	8150d 22h	/pci/tags/rel_6/apps/crt/syn/
25	* empty log message *	mihad	8171d 13h	/pci/tags/rel_6/apps/crt/syn/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8171d 16h	/pci/tags/rel_6/apps/crt/syn/
2	New project directory structure	mihad	8293d 16h	/pci/tags/rel_6/apps/crt/syn/