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[/] [pci/] [tags/] [rel_6/] [apps/] [crt/] [syn/] - Rev 90

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Rev Log message Author Age Path
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7762d 21h /pci/tags/rel_6/apps/crt/syn/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7862d 17h /pci/tags/rel_6/apps/crt/syn/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7865d 17h /pci/tags/rel_6/apps/crt/syn/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7981d 18h /pci/tags/rel_6/apps/crt/syn/
29 Xilinx synthesys log file tadej 8202d 01h /pci/tags/rel_6/apps/crt/syn/
25 *** empty log message *** mihad 8222d 16h /pci/tags/rel_6/apps/crt/syn/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8222d 19h /pci/tags/rel_6/apps/crt/syn/
2 New project directory structure mihad 8344d 18h /pci/tags/rel_6/apps/crt/syn/

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