OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [rtl/] - Rev 110

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7623d 17h /pci/tags/rel_6/rtl/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7627d 14h /pci/tags/rel_6/rtl/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7632d 13h /pci/tags/rel_6/rtl/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7637d 22h /pci/tags/rel_6/rtl/
94 Changed one critical PCI bus signal logic. mihad 7684d 21h /pci/tags/rel_6/rtl/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7762d 18h /pci/tags/rel_6/rtl/
86 Entered the option to disable no response counter in wb master. mihad 7774d 15h /pci/tags/rel_6/rtl/
83 Cleaned up the code. No functional changes. mihad 7803d 12h /pci/tags/rel_6/rtl/
81 Updated synchronization in top level fifo modules. mihad 7817d 09h /pci/tags/rel_6/rtl/
79 Updated. mihad 7820d 14h /pci/tags/rel_6/rtl/
78 Old files with wrong names removed. mihad 7820d 14h /pci/tags/rel_6/rtl/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7820d 14h /pci/tags/rel_6/rtl/
73 Bug fixes, testcases added. mihad 7826d 15h /pci/tags/rel_6/rtl/
72 *** empty log message *** mihad 7873d 18h /pci/tags/rel_6/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7881d 10h /pci/tags/rel_6/rtl/
69 Changed BIST signal names etc.. mihad 7918d 18h /pci/tags/rel_6/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7922d 03h /pci/tags/rel_6/rtl/
67 Changed BIST signals for RAMs. tadejm 7922d 08h /pci/tags/rel_6/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7925d 18h /pci/tags/rel_6/rtl/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7928d 17h /pci/tags/rel_6/rtl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.