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[/] [pci/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 53

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Rev Log message Author Age Path
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8012d 06h /pci/tags/rel_6/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8012d 10h /pci/tags/rel_6/rtl/verilog/
50 Got rid of undef directives mihad 8015d 02h /pci/tags/rel_6/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8015d 03h /pci/tags/rel_6/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8015d 03h /pci/tags/rel_6/rtl/verilog/
47 Known issues repaired mihad 8015d 08h /pci/tags/rel_6/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8020d 03h /pci/tags/rel_6/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8021d 08h /pci/tags/rel_6/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8166d 12h /pci/tags/rel_6/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8182d 07h /pci/tags/rel_6/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8190d 04h /pci/tags/rel_6/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8196d 03h /pci/tags/rel_6/rtl/verilog/
23 *** empty log message *** mihad 8214d 03h /pci/tags/rel_6/rtl/verilog/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8214d 04h /pci/tags/rel_6/rtl/verilog/
19 *** empty log message *** mihad 8214d 04h /pci/tags/rel_6/rtl/verilog/
18 *** empty log message *** mihad 8214d 05h /pci/tags/rel_6/rtl/verilog/
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8333d 11h /pci/tags/rel_6/rtl/verilog/
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8333d 11h /pci/tags/rel_6/rtl/verilog/
2 New project directory structure mihad 8336d 04h /pci/tags/rel_6/rtl/verilog/

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