URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [sim/] - Rev 106

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7635d 06h	/pci/tags/rel_6/sim/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7640d 16h	/pci/tags/rel_6/sim/
95	Removed this file, because it was too large - long download time.	mihad	7687d 14h	/pci/tags/rel_6/sim/
92	Update!	mihad	7687d 22h	/pci/tags/rel_6/sim/
81	Updated synchronization in top level fifo modules.	mihad	7820d 02h	/pci/tags/rel_6/sim/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7823d 07h	/pci/tags/rel_6/sim/
73	Bug fixes, testcases added.	mihad	7829d 08h	/pci/tags/rel_6/sim/
72	* empty log message *	mihad	7876d 12h	/pci/tags/rel_6/sim/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7931d 14h	/pci/tags/rel_6/sim/
62	Added BIST signals for RAMs.	mihad	7934d 07h	/pci/tags/rel_6/sim/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7942d 07h	/pci/tags/rel_6/sim/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7942d 08h	/pci/tags/rel_6/sim/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7981d 15h	/pci/tags/rel_6/sim/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7984d 07h	/pci/tags/rel_6/sim/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7990d 13h	/pci/tags/rel_6/sim/
42	Removed out of date files	mihad	8002d 14h	/pci/tags/rel_6/sim/
30	Example of PCI testbench log file	mihad	8162d 12h	/pci/tags/rel_6/sim/
27	Modified testbench and fixed some bugs	mihad	8165d 07h	/pci/tags/rel_6/sim/
26	Modified testbench and fixed some bugs	mihad	8165d 08h	/pci/tags/rel_6/sim/
22	Added short description for simulation running	mihad	8183d 08h	/pci/tags/rel_6/sim/

1 2 Next >

Show All

Browse

Tools

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [sim/] - Rev 106

Filtering Options