URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim/] - Rev 60

Rev	Log message	Author	Age	Path
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7936d 09h	/pci/tags/rel_6/sim/rtl_sim/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7936d 10h	/pci/tags/rel_6/sim/rtl_sim/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7975d 17h	/pci/tags/rel_6/sim/rtl_sim/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7978d 09h	/pci/tags/rel_6/sim/rtl_sim/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7984d 15h	/pci/tags/rel_6/sim/rtl_sim/
42	Removed out of date files	mihad	7996d 16h	/pci/tags/rel_6/sim/rtl_sim/
30	Example of PCI testbench log file	mihad	8156d 14h	/pci/tags/rel_6/sim/rtl_sim/
27	Modified testbench and fixed some bugs	mihad	8159d 09h	/pci/tags/rel_6/sim/rtl_sim/
26	Modified testbench and fixed some bugs	mihad	8159d 10h	/pci/tags/rel_6/sim/rtl_sim/
22	Added short description for simulation running	mihad	8177d 10h	/pci/tags/rel_6/sim/rtl_sim/
17	* empty log message *	mihad	8177d 12h	/pci/tags/rel_6/sim/rtl_sim/
16	Import of various scripts for simulation running	mihad	8177d 12h	/pci/tags/rel_6/sim/rtl_sim/