OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim/] [bin/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5577d 14h /pci/tags/rel_6/sim/rtl_sim/bin/
112 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7612d 09h /pci/tags/rel_6/sim/rtl_sim/bin/
109 There was missing path to hdl.var file. tadejm 7618d 06h /pci/tags/rel_6/sim/rtl_sim/bin/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7623d 04h /pci/tags/rel_6/sim/rtl_sim/bin/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7811d 05h /pci/tags/rel_6/sim/rtl_sim/bin/
62 Added BIST signals for RAMs. mihad 7922d 05h /pci/tags/rel_6/sim/rtl_sim/bin/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7930d 05h /pci/tags/rel_6/sim/rtl_sim/bin/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7930d 06h /pci/tags/rel_6/sim/rtl_sim/bin/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7972d 05h /pci/tags/rel_6/sim/rtl_sim/bin/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7978d 11h /pci/tags/rel_6/sim/rtl_sim/bin/
27 Modified testbench and fixed some bugs mihad 8153d 05h /pci/tags/rel_6/sim/rtl_sim/bin/
26 Modified testbench and fixed some bugs mihad 8153d 06h /pci/tags/rel_6/sim/rtl_sim/bin/
16 Import of various scripts for simulation running mihad 8171d 08h /pci/tags/rel_6/sim/rtl_sim/bin/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.