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[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim/] [run/] - Rev 106

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Rev	Log message	Author	Age	Path
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7648d 14h	/pci/tags/rel_6/sim/rtl_sim/run/
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7654d 00h	/pci/tags/rel_6/sim/rtl_sim/run/
92	Update!	mihad	7701d 06h	/pci/tags/rel_6/sim/rtl_sim/run/
81	Updated synchronization in top level fifo modules.	mihad	7833d 10h	/pci/tags/rel_6/sim/rtl_sim/run/
73	Bug fixes, testcases added.	mihad	7842d 16h	/pci/tags/rel_6/sim/rtl_sim/run/
72	* empty log message *	mihad	7889d 20h	/pci/tags/rel_6/sim/rtl_sim/run/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7944d 22h	/pci/tags/rel_6/sim/rtl_sim/run/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7955d 15h	/pci/tags/rel_6/sim/rtl_sim/run/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7994d 23h	/pci/tags/rel_6/sim/rtl_sim/run/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8003d 21h	/pci/tags/rel_6/sim/rtl_sim/run/
42	Removed out of date files	mihad	8015d 22h	/pci/tags/rel_6/sim/rtl_sim/run/
26	Modified testbench and fixed some bugs	mihad	8178d 16h	/pci/tags/rel_6/sim/rtl_sim/run/
22	Added short description for simulation running	mihad	8196d 16h	/pci/tags/rel_6/sim/rtl_sim/run/
17	* empty log message *	mihad	8196d 18h	/pci/tags/rel_6/sim/rtl_sim/run/

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