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[/] [pci/] [tags/] [rel_7/] - Rev 86

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Rev Log message Author Age Path
86 Entered the option to disable no response counter in wb master. mihad 7764d 22h /pci/tags/rel_7/
85 Changed Vendor ID defines. mihad 7765d 03h /pci/tags/rel_7/
84 Changed vendor ID. mihad 7768d 21h /pci/tags/rel_7/
83 Cleaned up the code. No functional changes. mihad 7793d 19h /pci/tags/rel_7/
81 Updated synchronization in top level fifo modules. mihad 7807d 16h /pci/tags/rel_7/
79 Updated. mihad 7810d 21h /pci/tags/rel_7/
78 Old files with wrong names removed. mihad 7810d 21h /pci/tags/rel_7/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7810d 21h /pci/tags/rel_7/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7813d 21h /pci/tags/rel_7/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7816d 21h /pci/tags/rel_7/
73 Bug fixes, testcases added. mihad 7816d 22h /pci/tags/rel_7/
72 *** empty log message *** mihad 7864d 02h /pci/tags/rel_7/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7871d 17h /pci/tags/rel_7/
69 Changed BIST signal names etc.. mihad 7909d 01h /pci/tags/rel_7/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7912d 10h /pci/tags/rel_7/
67 Changed BIST signals for RAMs. tadejm 7912d 15h /pci/tags/rel_7/
66 Changed empty status generation in pciw_fifo_control.v mihad 7916d 01h /pci/tags/rel_7/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7919d 00h /pci/tags/rel_7/
64 The testcase I just added in previous revision repaired mihad 7919d 02h /pci/tags/rel_7/
63 Added additional testcase and changed rst name in BIST to trst mihad 7919d 04h /pci/tags/rel_7/

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