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[/] [pci/] [tags/] [rel_7/] [bench/] [verilog/] - Rev 63

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Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7930d 06h /pci/tags/rel_7/bench/verilog/
62 Added BIST signals for RAMs. mihad 7932d 23h /pci/tags/rel_7/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7946d 06h /pci/tags/rel_7/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7979d 23h /pci/tags/rel_7/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7980d 07h /pci/tags/rel_7/bench/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7980d 07h /pci/tags/rel_7/bench/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7989d 05h /pci/tags/rel_7/bench/verilog/
44 Added for testing of Configuration Cycles Type 1 mihad 7989d 06h /pci/tags/rel_7/bench/verilog/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 7989d 06h /pci/tags/rel_7/bench/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8134d 09h /pci/tags/rel_7/bench/verilog/
34 Added missing include statements mihad 8149d 07h /pci/tags/rel_7/bench/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8150d 04h /pci/tags/rel_7/bench/verilog/
26 Modified testbench and fixed some bugs mihad 8164d 00h /pci/tags/rel_7/bench/verilog/
19 *** empty log message *** mihad 8182d 01h /pci/tags/rel_7/bench/verilog/
15 Initial testbench import. Still under development mihad 8182d 02h /pci/tags/rel_7/bench/verilog/
3 New project directory structure mihad 8304d 00h /pci/tags/rel_7/bench/verilog/

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