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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5552d 22h /pci/tags/rel_7/rtl/verilog/
114 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7587d 12h /pci/tags/rel_7/rtl/verilog/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7587d 12h /pci/tags/rel_7/rtl/verilog/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7587d 17h /pci/tags/rel_7/rtl/verilog/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7589d 16h /pci/tags/rel_7/rtl/verilog/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7593d 14h /pci/tags/rel_7/rtl/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7598d 12h /pci/tags/rel_7/rtl/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7603d 22h /pci/tags/rel_7/rtl/verilog/
94 Changed one critical PCI bus signal logic. mihad 7650d 20h /pci/tags/rel_7/rtl/verilog/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7728d 17h /pci/tags/rel_7/rtl/verilog/
86 Entered the option to disable no response counter in wb master. mihad 7740d 15h /pci/tags/rel_7/rtl/verilog/
83 Cleaned up the code. No functional changes. mihad 7769d 12h /pci/tags/rel_7/rtl/verilog/
81 Updated synchronization in top level fifo modules. mihad 7783d 08h /pci/tags/rel_7/rtl/verilog/
79 Updated. mihad 7786d 13h /pci/tags/rel_7/rtl/verilog/
78 Old files with wrong names removed. mihad 7786d 14h /pci/tags/rel_7/rtl/verilog/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7786d 14h /pci/tags/rel_7/rtl/verilog/
73 Bug fixes, testcases added. mihad 7792d 14h /pci/tags/rel_7/rtl/verilog/
72 *** empty log message *** mihad 7839d 18h /pci/tags/rel_7/rtl/verilog/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7847d 10h /pci/tags/rel_7/rtl/verilog/
69 Changed BIST signal names etc.. mihad 7884d 17h /pci/tags/rel_7/rtl/verilog/

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