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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 47

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Rev Log message Author Age Path
47 Known issues repaired mihad 8001d 17h /pci/tags/rel_7/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8006d 11h /pci/tags/rel_7/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8007d 16h /pci/tags/rel_7/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8152d 20h /pci/tags/rel_7/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8168d 16h /pci/tags/rel_7/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8176d 12h /pci/tags/rel_7/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8182d 11h /pci/tags/rel_7/rtl/verilog/
23 *** empty log message *** mihad 8200d 12h /pci/tags/rel_7/rtl/verilog/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8200d 12h /pci/tags/rel_7/rtl/verilog/
19 *** empty log message *** mihad 8200d 12h /pci/tags/rel_7/rtl/verilog/
18 *** empty log message *** mihad 8200d 13h /pci/tags/rel_7/rtl/verilog/
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8319d 19h /pci/tags/rel_7/rtl/verilog/
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8319d 19h /pci/tags/rel_7/rtl/verilog/
2 New project directory structure mihad 8322d 12h /pci/tags/rel_7/rtl/verilog/

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