OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 53

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7982d 09h /pci/tags/rel_7/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7982d 13h /pci/tags/rel_7/rtl/verilog/
50 Got rid of undef directives mihad 7985d 05h /pci/tags/rel_7/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7985d 05h /pci/tags/rel_7/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7985d 05h /pci/tags/rel_7/rtl/verilog/
47 Known issues repaired mihad 7985d 11h /pci/tags/rel_7/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 7990d 05h /pci/tags/rel_7/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7991d 11h /pci/tags/rel_7/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8136d 15h /pci/tags/rel_7/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8152d 10h /pci/tags/rel_7/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8160d 07h /pci/tags/rel_7/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8166d 06h /pci/tags/rel_7/rtl/verilog/
23 *** empty log message *** mihad 8184d 06h /pci/tags/rel_7/rtl/verilog/
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8184d 07h /pci/tags/rel_7/rtl/verilog/
19 *** empty log message *** mihad 8184d 07h /pci/tags/rel_7/rtl/verilog/
18 *** empty log message *** mihad 8184d 07h /pci/tags/rel_7/rtl/verilog/
7 Updated all files with inclusion of timescale file for simulation purposes. mihad 8303d 14h /pci/tags/rel_7/rtl/verilog/
6 Updated all files with inclusion of timescale file for simulation purposes. mihad 8303d 14h /pci/tags/rel_7/rtl/verilog/
2 New project directory structure mihad 8306d 07h /pci/tags/rel_7/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.