OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 63

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Added additional testcase and changed rst name in BIST to trst mihad 7962d 11h /pci/tags/rel_7/rtl/verilog/
62 Added BIST signals for RAMs. mihad 7965d 04h /pci/tags/rel_7/rtl/verilog/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7973d 04h /pci/tags/rel_7/rtl/verilog/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7973d 05h /pci/tags/rel_7/rtl/verilog/
58 Removed all logic from asynchronous reset network mihad 7978d 05h /pci/tags/rel_7/rtl/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7978d 11h /pci/tags/rel_7/rtl/verilog/
56 Number of state bits define was removed mihad 7979d 02h /pci/tags/rel_7/rtl/verilog/
55 Changed state machine encoding to true one-hot mihad 7979d 03h /pci/tags/rel_7/rtl/verilog/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8012d 08h /pci/tags/rel_7/rtl/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8012d 12h /pci/tags/rel_7/rtl/verilog/
50 Got rid of undef directives mihad 8015d 04h /pci/tags/rel_7/rtl/verilog/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8015d 04h /pci/tags/rel_7/rtl/verilog/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8015d 04h /pci/tags/rel_7/rtl/verilog/
47 Known issues repaired mihad 8015d 10h /pci/tags/rel_7/rtl/verilog/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8020d 04h /pci/tags/rel_7/rtl/verilog/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8021d 10h /pci/tags/rel_7/rtl/verilog/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8166d 14h /pci/tags/rel_7/rtl/verilog/
33 Added some testcases, removed un-needed fifo signals mihad 8182d 09h /pci/tags/rel_7/rtl/verilog/
32 Added include statement that was missing and causing errors mihad 8190d 06h /pci/tags/rel_7/rtl/verilog/
26 Modified testbench and fixed some bugs mihad 8196d 05h /pci/tags/rel_7/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.