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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 69

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Rev	Log message	Author	Age	Path
69	Changed BIST signal names etc..	mihad	7916d 22h	/pci/tags/rel_7/rtl/verilog/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7920d 08h	/pci/tags/rel_7/rtl/verilog/
67	Changed BIST signals for RAMs.	tadejm	7920d 13h	/pci/tags/rel_7/rtl/verilog/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7923d 23h	/pci/tags/rel_7/rtl/verilog/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7926d 21h	/pci/tags/rel_7/rtl/verilog/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7927d 01h	/pci/tags/rel_7/rtl/verilog/
62	Added BIST signals for RAMs.	mihad	7929d 18h	/pci/tags/rel_7/rtl/verilog/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7937d 18h	/pci/tags/rel_7/rtl/verilog/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7937d 19h	/pci/tags/rel_7/rtl/verilog/
58	Removed all logic from asynchronous reset network	mihad	7942d 20h	/pci/tags/rel_7/rtl/verilog/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7943d 02h	/pci/tags/rel_7/rtl/verilog/
56	Number of state bits define was removed	mihad	7943d 16h	/pci/tags/rel_7/rtl/verilog/
55	Changed state machine encoding to true one-hot	mihad	7943d 17h	/pci/tags/rel_7/rtl/verilog/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	7976d 22h	/pci/tags/rel_7/rtl/verilog/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7977d 02h	/pci/tags/rel_7/rtl/verilog/
50	Got rid of undef directives	mihad	7979d 19h	/pci/tags/rel_7/rtl/verilog/
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7979d 19h	/pci/tags/rel_7/rtl/verilog/
48	Extracted distributed RAM module from wb/pci_tpram.v to its own file	mihad	7979d 19h	/pci/tags/rel_7/rtl/verilog/
47	Known issues repaired	mihad	7980d 01h	/pci/tags/rel_7/rtl/verilog/
46	Include statement was enclosed in synosys translate off/on directive - repaired	mihad	7984d 19h	/pci/tags/rel_7/rtl/verilog/

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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 69

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