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[/] [pci/] [tags/] [rel_7/] [sim/] - Rev 73

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Rev Log message Author Age Path
73 Bug fixes, testcases added. mihad 7827d 04h /pci/tags/rel_7/sim/
72 *** empty log message *** mihad 7874d 08h /pci/tags/rel_7/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7929d 10h /pci/tags/rel_7/sim/
62 Added BIST signals for RAMs. mihad 7932d 03h /pci/tags/rel_7/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7940d 03h /pci/tags/rel_7/sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7940d 04h /pci/tags/rel_7/sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7979d 11h /pci/tags/rel_7/sim/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7982d 03h /pci/tags/rel_7/sim/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7988d 09h /pci/tags/rel_7/sim/
42 Removed out of date files mihad 8000d 10h /pci/tags/rel_7/sim/
30 Example of PCI testbench log file mihad 8160d 08h /pci/tags/rel_7/sim/
27 Modified testbench and fixed some bugs mihad 8163d 03h /pci/tags/rel_7/sim/
26 Modified testbench and fixed some bugs mihad 8163d 04h /pci/tags/rel_7/sim/
22 Added short description for simulation running mihad 8181d 04h /pci/tags/rel_7/sim/
20 *** empty log message *** mihad 8181d 05h /pci/tags/rel_7/sim/
17 *** empty log message *** mihad 8181d 06h /pci/tags/rel_7/sim/
16 Import of various scripts for simulation running mihad 8181d 06h /pci/tags/rel_7/sim/
3 New project directory structure mihad 8303d 04h /pci/tags/rel_7/sim/

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