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[/] [pci/] [tags/] [rel_8/] - Rev 81

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Rev	Log message	Author	Age	Path
81	Updated synchronization in top level fifo modules.	mihad	7812d 03h	/pci/tags/rel_8/
79	Updated.	mihad	7815d 07h	/pci/tags/rel_8/
78	Old files with wrong names removed.	mihad	7815d 08h	/pci/tags/rel_8/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7815d 08h	/pci/tags/rel_8/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7818d 07h	/pci/tags/rel_8/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7821d 08h	/pci/tags/rel_8/
73	Bug fixes, testcases added.	mihad	7821d 08h	/pci/tags/rel_8/
72	* empty log message *	mihad	7868d 12h	/pci/tags/rel_8/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7876d 04h	/pci/tags/rel_8/
69	Changed BIST signal names etc..	mihad	7913d 12h	/pci/tags/rel_8/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7916d 21h	/pci/tags/rel_8/
67	Changed BIST signals for RAMs.	tadejm	7917d 02h	/pci/tags/rel_8/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7920d 12h	/pci/tags/rel_8/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7923d 10h	/pci/tags/rel_8/
64	The testcase I just added in previous revision repaired	mihad	7923d 13h	/pci/tags/rel_8/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7923d 14h	/pci/tags/rel_8/
62	Added BIST signals for RAMs.	mihad	7926d 07h	/pci/tags/rel_8/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7934d 07h	/pci/tags/rel_8/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7934d 09h	/pci/tags/rel_8/
58	Removed all logic from asynchronous reset network	mihad	7939d 09h	/pci/tags/rel_8/

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[/] [pci/] [tags/] [rel_8/] - Rev 81

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