URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [apps/] [crt/] - Rev 120

Rev	Log message	Author	Age	Path
120	This commit was manufactured by cvs2svn to create tag 'rel_8'.		7656d 17h	/pci/tags/rel_8/apps/crt/
96	Update!	mihad	7727d 03h	/pci/tags/rel_8/apps/crt/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7763d 01h	/pci/tags/rel_8/apps/crt/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7763d 01h	/pci/tags/rel_8/apps/crt/
84	Changed vendor ID.	mihad	7820d 21h	/pci/tags/rel_8/apps/crt/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7862d 21h	/pci/tags/rel_8/apps/crt/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7865d 20h	/pci/tags/rel_8/apps/crt/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7868d 21h	/pci/tags/rel_8/apps/crt/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7981d 22h	/pci/tags/rel_8/apps/crt/
31	User defined constants used for Test Application	tadej	8201d 17h	/pci/tags/rel_8/apps/crt/
29	Xilinx synthesys log file	tadej	8202d 04h	/pci/tags/rel_8/apps/crt/
25	* empty log message *	mihad	8222d 20h	/pci/tags/rel_8/apps/crt/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8222d 22h	/pci/tags/rel_8/apps/crt/
14	* empty log message *	mihad	8223d 00h	/pci/tags/rel_8/apps/crt/
2	New project directory structure	mihad	8344d 22h	/pci/tags/rel_8/apps/crt/