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[/] [pci/] [tags/] [rel_8/] [bench/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5565d 20h /pci/tags/rel_8/bench/verilog/
120 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7593d 08h /pci/tags/rel_8/bench/verilog/
119 Added support for WB B3. Some testcases were updated. tadejm 7593d 08h /pci/tags/rel_8/bench/verilog/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7606d 12h /pci/tags/rel_8/bench/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7611d 11h /pci/tags/rel_8/bench/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7616d 21h /pci/tags/rel_8/bench/verilog/
92 Update! mihad 7664d 02h /pci/tags/rel_8/bench/verilog/
89 Burst 2 error fixed. mihad 7735d 17h /pci/tags/rel_8/bench/verilog/
87 Updated acording to RTL changes. mihad 7753d 13h /pci/tags/rel_8/bench/verilog/
81 Updated synchronization in top level fifo modules. mihad 7796d 07h /pci/tags/rel_8/bench/verilog/
73 Bug fixes, testcases added. mihad 7805d 13h /pci/tags/rel_8/bench/verilog/
69 Changed BIST signal names etc.. mihad 7897d 16h /pci/tags/rel_8/bench/verilog/
66 Changed empty status generation in pciw_fifo_control.v mihad 7904d 16h /pci/tags/rel_8/bench/verilog/
64 The testcase I just added in previous revision repaired mihad 7907d 17h /pci/tags/rel_8/bench/verilog/
63 Added additional testcase and changed rst name in BIST to trst mihad 7907d 19h /pci/tags/rel_8/bench/verilog/
62 Added BIST signals for RAMs. mihad 7910d 12h /pci/tags/rel_8/bench/verilog/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7923d 19h /pci/tags/rel_8/bench/verilog/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7957d 12h /pci/tags/rel_8/bench/verilog/
52 Oops, never before noticed that OC header is missing mihad 7957d 20h /pci/tags/rel_8/bench/verilog/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7957d 20h /pci/tags/rel_8/bench/verilog/

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