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[/] [pci/] [tags/] [rel_8/] [rtl/] - Rev 108

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Rev Log message Author Age Path
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7617d 00h /pci/tags/rel_8/rtl/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7621d 23h /pci/tags/rel_8/rtl/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7627d 08h /pci/tags/rel_8/rtl/
94 Changed one critical PCI bus signal logic. mihad 7674d 07h /pci/tags/rel_8/rtl/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.
mihad 7752d 04h /pci/tags/rel_8/rtl/
86 Entered the option to disable no response counter in wb master. mihad 7764d 01h /pci/tags/rel_8/rtl/
83 Cleaned up the code. No functional changes. mihad 7792d 22h /pci/tags/rel_8/rtl/
81 Updated synchronization in top level fifo modules. mihad 7806d 19h /pci/tags/rel_8/rtl/
79 Updated. mihad 7810d 00h /pci/tags/rel_8/rtl/
78 Old files with wrong names removed. mihad 7810d 00h /pci/tags/rel_8/rtl/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7810d 00h /pci/tags/rel_8/rtl/
73 Bug fixes, testcases added. mihad 7816d 01h /pci/tags/rel_8/rtl/
72 *** empty log message *** mihad 7863d 05h /pci/tags/rel_8/rtl/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7870d 20h /pci/tags/rel_8/rtl/
69 Changed BIST signal names etc.. mihad 7908d 04h /pci/tags/rel_8/rtl/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7911d 13h /pci/tags/rel_8/rtl/
67 Changed BIST signals for RAMs. tadejm 7911d 18h /pci/tags/rel_8/rtl/
66 Changed empty status generation in pciw_fifo_control.v mihad 7915d 04h /pci/tags/rel_8/rtl/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7918d 03h /pci/tags/rel_8/rtl/
63 Added additional testcase and changed rst name in BIST to trst mihad 7918d 07h /pci/tags/rel_8/rtl/

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