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[/] [pci/] [tags/] [rel_8/] [rtl/] - Rev 83

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Rev	Log message	Author	Age	Path
83	Cleaned up the code. No functional changes.	mihad	7794d 00h	/pci/tags/rel_8/rtl/
81	Updated synchronization in top level fifo modules.	mihad	7807d 20h	/pci/tags/rel_8/rtl/
79	Updated.	mihad	7811d 01h	/pci/tags/rel_8/rtl/
78	Old files with wrong names removed.	mihad	7811d 01h	/pci/tags/rel_8/rtl/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7811d 01h	/pci/tags/rel_8/rtl/
73	Bug fixes, testcases added.	mihad	7817d 02h	/pci/tags/rel_8/rtl/
72	* empty log message *	mihad	7864d 06h	/pci/tags/rel_8/rtl/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7871d 22h	/pci/tags/rel_8/rtl/
69	Changed BIST signal names etc..	mihad	7909d 05h	/pci/tags/rel_8/rtl/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7912d 15h	/pci/tags/rel_8/rtl/
67	Changed BIST signals for RAMs.	tadejm	7912d 19h	/pci/tags/rel_8/rtl/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7916d 06h	/pci/tags/rel_8/rtl/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7919d 04h	/pci/tags/rel_8/rtl/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7919d 08h	/pci/tags/rel_8/rtl/
62	Added BIST signals for RAMs.	mihad	7922d 01h	/pci/tags/rel_8/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7930d 01h	/pci/tags/rel_8/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7930d 02h	/pci/tags/rel_8/rtl/
58	Removed all logic from asynchronous reset network	mihad	7935d 02h	/pci/tags/rel_8/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7935d 08h	/pci/tags/rel_8/rtl/
56	Number of state bits define was removed	mihad	7935d 23h	/pci/tags/rel_8/rtl/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_8/] [rtl/] - Rev 83

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