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[/] [pci/] [tags/] [rel_8/] [rtl/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5556d 02h /pci/tags/rel_8/rtl/verilog/
120 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7583d 13h /pci/tags/rel_8/rtl/verilog/
117 WB Master is now WISHBONE B3 compatible. tadejm 7583d 13h /pci/tags/rel_8/rtl/verilog/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7583d 13h /pci/tags/rel_8/rtl/verilog/
115 Added signals for WB Master B3. tadejm 7583d 13h /pci/tags/rel_8/rtl/verilog/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7590d 16h /pci/tags/rel_8/rtl/verilog/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7590d 21h /pci/tags/rel_8/rtl/verilog/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7592d 20h /pci/tags/rel_8/rtl/verilog/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7596d 18h /pci/tags/rel_8/rtl/verilog/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7601d 16h /pci/tags/rel_8/rtl/verilog/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7607d 02h /pci/tags/rel_8/rtl/verilog/
94 Changed one critical PCI bus signal logic. mihad 7654d 00h /pci/tags/rel_8/rtl/verilog/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7731d 21h /pci/tags/rel_8/rtl/verilog/
86 Entered the option to disable no response counter in wb master. mihad 7743d 19h /pci/tags/rel_8/rtl/verilog/
83 Cleaned up the code. No functional changes. mihad 7772d 16h /pci/tags/rel_8/rtl/verilog/
81 Updated synchronization in top level fifo modules. mihad 7786d 12h /pci/tags/rel_8/rtl/verilog/
79 Updated. mihad 7789d 17h /pci/tags/rel_8/rtl/verilog/
78 Old files with wrong names removed. mihad 7789d 17h /pci/tags/rel_8/rtl/verilog/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7789d 17h /pci/tags/rel_8/rtl/verilog/
73 Bug fixes, testcases added. mihad 7795d 18h /pci/tags/rel_8/rtl/verilog/

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