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[/] [pci/] [tags/] [rel_9/] - Rev 79

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Rev	Log message	Author	Age	Path
79	Updated.	mihad	7861d 21h	/pci/tags/rel_9/
78	Old files with wrong names removed.	mihad	7861d 22h	/pci/tags/rel_9/
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7861d 22h	/pci/tags/rel_9/
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7864d 21h	/pci/tags/rel_9/
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7867d 22h	/pci/tags/rel_9/
73	Bug fixes, testcases added.	mihad	7867d 22h	/pci/tags/rel_9/
72	* empty log message *	mihad	7915d 02h	/pci/tags/rel_9/
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7922d 18h	/pci/tags/rel_9/
69	Changed BIST signal names etc..	mihad	7960d 01h	/pci/tags/rel_9/
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7963d 11h	/pci/tags/rel_9/
67	Changed BIST signals for RAMs.	tadejm	7963d 16h	/pci/tags/rel_9/
66	Changed empty status generation in pciw_fifo_control.v	mihad	7967d 02h	/pci/tags/rel_9/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7970d 00h	/pci/tags/rel_9/
64	The testcase I just added in previous revision repaired	mihad	7970d 02h	/pci/tags/rel_9/
63	Added additional testcase and changed rst name in BIST to trst	mihad	7970d 04h	/pci/tags/rel_9/
62	Added BIST signals for RAMs.	mihad	7972d 21h	/pci/tags/rel_9/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7980d 21h	/pci/tags/rel_9/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7980d 22h	/pci/tags/rel_9/
58	Removed all logic from asynchronous reset network	mihad	7985d 23h	/pci/tags/rel_9/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	7986d 05h	/pci/tags/rel_9/

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[/] [pci/] [tags/] [rel_9/] - Rev 79

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