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[/] [pci/] [tags/] [rel_9/] - Rev 94

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Rev Log message Author Age Path
94 Changed one critical PCI bus signal logic. mihad 7676d 09h /pci/tags/rel_9/
93 Added a test application! mihad 7676d 16h /pci/tags/rel_9/
92 Update! mihad 7676d 16h /pci/tags/rel_9/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7712d 06h /pci/tags/rel_9/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7712d 06h /pci/tags/rel_9/
89 Burst 2 error fixed. mihad 7748d 07h /pci/tags/rel_9/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7754d 06h /pci/tags/rel_9/
87 Updated acording to RTL changes. mihad 7766d 03h /pci/tags/rel_9/
86 Entered the option to disable no response counter in wb master. mihad 7766d 03h /pci/tags/rel_9/
85 Changed Vendor ID defines. mihad 7766d 08h /pci/tags/rel_9/
84 Changed vendor ID. mihad 7770d 02h /pci/tags/rel_9/
83 Cleaned up the code. No functional changes. mihad 7795d 00h /pci/tags/rel_9/
81 Updated synchronization in top level fifo modules. mihad 7808d 21h /pci/tags/rel_9/
79 Updated. mihad 7812d 02h /pci/tags/rel_9/
78 Old files with wrong names removed. mihad 7812d 02h /pci/tags/rel_9/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7812d 02h /pci/tags/rel_9/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7815d 02h /pci/tags/rel_9/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7818d 03h /pci/tags/rel_9/
73 Bug fixes, testcases added. mihad 7818d 03h /pci/tags/rel_9/
72 *** empty log message *** mihad 7865d 07h /pci/tags/rel_9/

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