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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 105

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Rev Log message Author Age Path
105 Wrong pci_bridge32.v file included in the project! mihad 7672d 07h /pci/tags/rel_WB_B3/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7672d 09h /pci/tags/rel_WB_B3/
103 Added test application and modified files to support it. mihad 7719d 06h /pci/tags/rel_WB_B3/
102 Cleanup! mihad 7719d 06h /pci/tags/rel_WB_B3/
101 Added simulation files. mihad 7719d 06h /pci/tags/rel_WB_B3/
100 Cleanup! mihad 7719d 06h /pci/tags/rel_WB_B3/
99 Cleanup! mihad 7719d 07h /pci/tags/rel_WB_B3/
98 Cleanup. mihad 7719d 07h /pci/tags/rel_WB_B3/
97 Doing a little bit of cleanup. mihad 7719d 07h /pci/tags/rel_WB_B3/
96 Update! mihad 7719d 07h /pci/tags/rel_WB_B3/
95 Removed this file, because it was too large - long download time. mihad 7719d 07h /pci/tags/rel_WB_B3/
94 Changed one critical PCI bus signal logic. mihad 7719d 07h /pci/tags/rel_WB_B3/
93 Added a test application! mihad 7719d 14h /pci/tags/rel_WB_B3/
92 Update! mihad 7719d 15h /pci/tags/rel_WB_B3/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7755d 05h /pci/tags/rel_WB_B3/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7755d 05h /pci/tags/rel_WB_B3/
89 Burst 2 error fixed. mihad 7791d 05h /pci/tags/rel_WB_B3/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7797d 04h /pci/tags/rel_WB_B3/
87 Updated acording to RTL changes. mihad 7809d 02h /pci/tags/rel_WB_B3/
86 Entered the option to disable no response counter in wb master. mihad 7809d 02h /pci/tags/rel_WB_B3/

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