URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 25

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Rev	Log message	Author	Age	Path
25	* empty log message *	mihad	8231d 17h	/pci/tags/rel_WB_B3/
24	* empty log message *	mihad	8231d 18h	/pci/tags/rel_WB_B3/
23	* empty log message *	mihad	8231d 19h	/pci/tags/rel_WB_B3/
22	Added short description for simulation running	mihad	8231d 19h	/pci/tags/rel_WB_B3/
21	Repaired a few bugs, updated specification, added test bench files and design document	mihad	8231d 20h	/pci/tags/rel_WB_B3/
20	* empty log message *	mihad	8231d 20h	/pci/tags/rel_WB_B3/
19	* empty log message *	mihad	8231d 20h	/pci/tags/rel_WB_B3/
18	* empty log message *	mihad	8231d 21h	/pci/tags/rel_WB_B3/
17	* empty log message *	mihad	8231d 21h	/pci/tags/rel_WB_B3/
16	Import of various scripts for simulation running	mihad	8231d 21h	/pci/tags/rel_WB_B3/
15	Initial testbench import. Still under development	mihad	8231d 22h	/pci/tags/rel_WB_B3/
14	* empty log message *	mihad	8231d 22h	/pci/tags/rel_WB_B3/
13	Added separate software directory to the project	mihad	8231d 22h	/pci/tags/rel_WB_B3/
12	PCI IP Core Introduction	mihad	8233d 18h	/pci/tags/rel_WB_B3/
11	Initial design document release	mihad	8233d 18h	/pci/tags/rel_WB_B3/
10	Updated descriptions, functional changes, added software obligations chapter	mihad	8233d 18h	/pci/tags/rel_WB_B3/
9	Update the Configuration Space and REGISTERS description	mihad	8334d 02h	/pci/tags/rel_WB_B3/
7	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8351d 03h	/pci/tags/rel_WB_B3/
6	Updated all files with inclusion of timescale file for simulation purposes.	mihad	8351d 03h	/pci/tags/rel_WB_B3/
5	Added .o file for kernel 2.4.3	mihad	8353d 18h	/pci/tags/rel_WB_B3/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 25

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