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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 45

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45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8071d 10h /pci/tags/rel_WB_B3/
44 Added for testing of Configuration Cycles Type 1 mihad 8071d 11h /pci/tags/rel_WB_B3/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8071d 11h /pci/tags/rel_WB_B3/
42 Removed out of date files mihad 8083d 11h /pci/tags/rel_WB_B3/
40 From these Wrod files PDF were created - added future improvements tadej 8162d 02h /pci/tags/rel_WB_B3/
39 File not needed tadej 8162d 03h /pci/tags/rel_WB_B3/
38 This file is not needed tadej 8162d 06h /pci/tags/rel_WB_B3/
37 These files are not needed any more tadej 8162d 06h /pci/tags/rel_WB_B3/
36 *** empty log message *** tadej 8162d 06h /pci/tags/rel_WB_B3/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8216d 14h /pci/tags/rel_WB_B3/
34 Added missing include statements mihad 8231d 12h /pci/tags/rel_WB_B3/
33 Added some testcases, removed un-needed fifo signals mihad 8232d 10h /pci/tags/rel_WB_B3/
32 Added include statement that was missing and causing errors mihad 8240d 06h /pci/tags/rel_WB_B3/
31 User defined constants used for Test Application tadej 8243d 01h /pci/tags/rel_WB_B3/
30 Example of PCI testbench log file mihad 8243d 09h /pci/tags/rel_WB_B3/
29 Xilinx synthesys log file tadej 8243d 12h /pci/tags/rel_WB_B3/
28 pci/doc/pci_databook.pdf tadej 8244d 07h /pci/tags/rel_WB_B3/
27 Modified testbench and fixed some bugs mihad 8246d 04h /pci/tags/rel_WB_B3/
26 Modified testbench and fixed some bugs mihad 8246d 05h /pci/tags/rel_WB_B3/
25 *** empty log message *** mihad 8264d 03h /pci/tags/rel_WB_B3/

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