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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 77

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Rev Log message Author Age Path
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7854d 02h /pci/tags/rel_WB_B3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7857d 01h /pci/tags/rel_WB_B3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7860d 02h /pci/tags/rel_WB_B3/
73 Bug fixes, testcases added. mihad 7860d 03h /pci/tags/rel_WB_B3/
72 *** empty log message *** mihad 7907d 06h /pci/tags/rel_WB_B3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7914d 22h /pci/tags/rel_WB_B3/
69 Changed BIST signal names etc.. mihad 7952d 06h /pci/tags/rel_WB_B3/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7955d 15h /pci/tags/rel_WB_B3/
67 Changed BIST signals for RAMs. tadejm 7955d 20h /pci/tags/rel_WB_B3/
66 Changed empty status generation in pciw_fifo_control.v mihad 7959d 06h /pci/tags/rel_WB_B3/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7962d 04h /pci/tags/rel_WB_B3/
64 The testcase I just added in previous revision repaired mihad 7962d 07h /pci/tags/rel_WB_B3/
63 Added additional testcase and changed rst name in BIST to trst mihad 7962d 08h /pci/tags/rel_WB_B3/
62 Added BIST signals for RAMs. mihad 7965d 01h /pci/tags/rel_WB_B3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7973d 01h /pci/tags/rel_WB_B3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7973d 03h /pci/tags/rel_WB_B3/
58 Removed all logic from asynchronous reset network mihad 7978d 03h /pci/tags/rel_WB_B3/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7978d 09h /pci/tags/rel_WB_B3/
56 Number of state bits define was removed mihad 7978d 23h /pci/tags/rel_WB_B3/
55 Changed state machine encoding to true one-hot mihad 7979d 00h /pci/tags/rel_WB_B3/

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