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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 90

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Rev Log message Author Age Path
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7711d 08h /pci/tags/rel_WB_B3/
89 Burst 2 error fixed. mihad 7747d 08h /pci/tags/rel_WB_B3/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7753d 07h /pci/tags/rel_WB_B3/
87 Updated acording to RTL changes. mihad 7765d 05h /pci/tags/rel_WB_B3/
86 Entered the option to disable no response counter in wb master. mihad 7765d 05h /pci/tags/rel_WB_B3/
85 Changed Vendor ID defines. mihad 7765d 09h /pci/tags/rel_WB_B3/
84 Changed vendor ID. mihad 7769d 03h /pci/tags/rel_WB_B3/
83 Cleaned up the code. No functional changes. mihad 7794d 02h /pci/tags/rel_WB_B3/
81 Updated synchronization in top level fifo modules. mihad 7807d 22h /pci/tags/rel_WB_B3/
79 Updated. mihad 7811d 03h /pci/tags/rel_WB_B3/
78 Old files with wrong names removed. mihad 7811d 04h /pci/tags/rel_WB_B3/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7811d 04h /pci/tags/rel_WB_B3/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7814d 03h /pci/tags/rel_WB_B3/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7817d 04h /pci/tags/rel_WB_B3/
73 Bug fixes, testcases added. mihad 7817d 04h /pci/tags/rel_WB_B3/
72 *** empty log message *** mihad 7864d 08h /pci/tags/rel_WB_B3/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7872d 00h /pci/tags/rel_WB_B3/
69 Changed BIST signal names etc.. mihad 7909d 07h /pci/tags/rel_WB_B3/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7912d 17h /pci/tags/rel_WB_B3/
67 Changed BIST signals for RAMs. tadejm 7912d 22h /pci/tags/rel_WB_B3/

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