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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 99

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Rev	Log message	Author	Age	Path
99	Cleanup!	mihad	7716d 10h	/pci/tags/rel_WB_B3/
98	Cleanup.	mihad	7716d 10h	/pci/tags/rel_WB_B3/
97	Doing a little bit of cleanup.	mihad	7716d 10h	/pci/tags/rel_WB_B3/
96	Update!	mihad	7716d 11h	/pci/tags/rel_WB_B3/
95	Removed this file, because it was too large - long download time.	mihad	7716d 11h	/pci/tags/rel_WB_B3/
94	Changed one critical PCI bus signal logic.	mihad	7716d 11h	/pci/tags/rel_WB_B3/
93	Added a test application!	mihad	7716d 18h	/pci/tags/rel_WB_B3/
92	Update!	mihad	7716d 18h	/pci/tags/rel_WB_B3/
91	WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7752d 08h	/pci/tags/rel_WB_B3/
90	WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de)	tadejm	7752d 08h	/pci/tags/rel_WB_B3/
89	Burst 2 error fixed.	mihad	7788d 09h	/pci/tags/rel_WB_B3/
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7794d 08h	/pci/tags/rel_WB_B3/
87	Updated acording to RTL changes.	mihad	7806d 05h	/pci/tags/rel_WB_B3/
86	Entered the option to disable no response counter in wb master.	mihad	7806d 05h	/pci/tags/rel_WB_B3/
85	Changed Vendor ID defines.	mihad	7806d 09h	/pci/tags/rel_WB_B3/
84	Changed vendor ID.	mihad	7810d 04h	/pci/tags/rel_WB_B3/
83	Cleaned up the code. No functional changes.	mihad	7835d 02h	/pci/tags/rel_WB_B3/
81	Updated synchronization in top level fifo modules.	mihad	7848d 23h	/pci/tags/rel_WB_B3/
79	Updated.	mihad	7852d 04h	/pci/tags/rel_WB_B3/
78	Old files with wrong names removed.	mihad	7852d 04h	/pci/tags/rel_WB_B3/

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Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 99

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