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[/] [pci/] [tags/] [rel_WB_B3/] [apps/] - Rev 102

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Rev Log message Author Age Path
102 Cleanup! mihad 7684d 13h /pci/tags/rel_WB_B3/apps/
101 Added simulation files. mihad 7684d 13h /pci/tags/rel_WB_B3/apps/
100 Cleanup! mihad 7684d 13h /pci/tags/rel_WB_B3/apps/
99 Cleanup! mihad 7684d 14h /pci/tags/rel_WB_B3/apps/
98 Cleanup. mihad 7684d 14h /pci/tags/rel_WB_B3/apps/
97 Doing a little bit of cleanup. mihad 7684d 14h /pci/tags/rel_WB_B3/apps/
96 Update! mihad 7684d 14h /pci/tags/rel_WB_B3/apps/
93 Added a test application! mihad 7684d 21h /pci/tags/rel_WB_B3/apps/
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7720d 12h /pci/tags/rel_WB_B3/apps/
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7720d 12h /pci/tags/rel_WB_B3/apps/
85 Changed Vendor ID defines. mihad 7774d 13h /pci/tags/rel_WB_B3/apps/
84 Changed vendor ID. mihad 7778d 07h /pci/tags/rel_WB_B3/apps/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7820d 08h /pci/tags/rel_WB_B3/apps/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7823d 07h /pci/tags/rel_WB_B3/apps/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7826d 08h /pci/tags/rel_WB_B3/apps/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7939d 08h /pci/tags/rel_WB_B3/apps/
38 This file is not needed tadej 8078d 08h /pci/tags/rel_WB_B3/apps/
36 *** empty log message *** tadej 8078d 09h /pci/tags/rel_WB_B3/apps/
31 User defined constants used for Test Application tadej 8159d 04h /pci/tags/rel_WB_B3/apps/
29 Xilinx synthesys log file tadej 8159d 15h /pci/tags/rel_WB_B3/apps/

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