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[/] [pci/] [tags/] [rel_WB_B3/] [bench/] - Rev 121

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Rev Log message Author Age Path
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7609d 21h /pci/tags/rel_WB_B3/bench/
119 Added support for WB B3. Some testcases were updated. tadejm 7609d 21h /pci/tags/rel_WB_B3/bench/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7623d 02h /pci/tags/rel_WB_B3/bench/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7628d 00h /pci/tags/rel_WB_B3/bench/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7633d 10h /pci/tags/rel_WB_B3/bench/
92 Update! mihad 7680d 16h /pci/tags/rel_WB_B3/bench/
89 Burst 2 error fixed. mihad 7752d 06h /pci/tags/rel_WB_B3/bench/
87 Updated acording to RTL changes. mihad 7770d 03h /pci/tags/rel_WB_B3/bench/
81 Updated synchronization in top level fifo modules. mihad 7812d 20h /pci/tags/rel_WB_B3/bench/
73 Bug fixes, testcases added. mihad 7822d 02h /pci/tags/rel_WB_B3/bench/
69 Changed BIST signal names etc.. mihad 7914d 05h /pci/tags/rel_WB_B3/bench/
66 Changed empty status generation in pciw_fifo_control.v mihad 7921d 06h /pci/tags/rel_WB_B3/bench/
64 The testcase I just added in previous revision repaired mihad 7924d 06h /pci/tags/rel_WB_B3/bench/
63 Added additional testcase and changed rst name in BIST to trst mihad 7924d 08h /pci/tags/rel_WB_B3/bench/
62 Added BIST signals for RAMs. mihad 7927d 01h /pci/tags/rel_WB_B3/bench/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7940d 08h /pci/tags/rel_WB_B3/bench/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7974d 01h /pci/tags/rel_WB_B3/bench/
52 Oops, never before noticed that OC header is missing mihad 7974d 09h /pci/tags/rel_WB_B3/bench/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7974d 09h /pci/tags/rel_WB_B3/bench/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7983d 07h /pci/tags/rel_WB_B3/bench/

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