URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [bench/] - Rev 54

Rev	Log message	Author	Age	Path
54	Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim	mihad	8071d 20h	/pci/tags/rel_WB_B3/bench/
52	Oops, never before noticed that OC header is missing	mihad	8072d 03h	/pci/tags/rel_WB_B3/bench/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8072d 04h	/pci/tags/rel_WB_B3/bench/
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	8081d 02h	/pci/tags/rel_WB_B3/bench/
44	Added for testing of Configuration Cycles Type 1	mihad	8081d 02h	/pci/tags/rel_WB_B3/bench/
43	Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device	mihad	8081d 02h	/pci/tags/rel_WB_B3/bench/
35	Files updated with missing includes, resolved some race conditions in test bench	mihad	8226d 05h	/pci/tags/rel_WB_B3/bench/
34	Added missing include statements	mihad	8241d 04h	/pci/tags/rel_WB_B3/bench/
33	Added some testcases, removed un-needed fifo signals	mihad	8242d 01h	/pci/tags/rel_WB_B3/bench/
26	Modified testbench and fixed some bugs	mihad	8255d 20h	/pci/tags/rel_WB_B3/bench/
19	* empty log message *	mihad	8273d 22h	/pci/tags/rel_WB_B3/bench/
15	Initial testbench import. Still under development	mihad	8273d 23h	/pci/tags/rel_WB_B3/bench/
3	New project directory structure	mihad	8395d 21h	/pci/tags/rel_WB_B3/bench/