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[/] [pci/] [tags/] [rel_WB_B3/] [sim/] - Rev 118

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Rev Log message Author Age Path
118 Some minor changes due to changes in core. tadejm 7625d 16h /pci/tags/rel_WB_B3/sim/
109 There was missing path to hdl.var file. tadejm 7638d 20h /pci/tags/rel_WB_B3/sim/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7643d 19h /pci/tags/rel_WB_B3/sim/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7649d 05h /pci/tags/rel_WB_B3/sim/
95 Removed this file, because it was too large - long download time. mihad 7696d 03h /pci/tags/rel_WB_B3/sim/
92 Update! mihad 7696d 10h /pci/tags/rel_WB_B3/sim/
81 Updated synchronization in top level fifo modules. mihad 7828d 15h /pci/tags/rel_WB_B3/sim/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7831d 20h /pci/tags/rel_WB_B3/sim/
73 Bug fixes, testcases added. mihad 7837d 21h /pci/tags/rel_WB_B3/sim/
72 *** empty log message *** mihad 7885d 01h /pci/tags/rel_WB_B3/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7940d 03h /pci/tags/rel_WB_B3/sim/
62 Added BIST signals for RAMs. mihad 7942d 20h /pci/tags/rel_WB_B3/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7950d 20h /pci/tags/rel_WB_B3/sim/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7950d 21h /pci/tags/rel_WB_B3/sim/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7990d 04h /pci/tags/rel_WB_B3/sim/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7992d 20h /pci/tags/rel_WB_B3/sim/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 7999d 02h /pci/tags/rel_WB_B3/sim/
42 Removed out of date files mihad 8011d 03h /pci/tags/rel_WB_B3/sim/
30 Example of PCI testbench log file mihad 8171d 01h /pci/tags/rel_WB_B3/sim/
27 Modified testbench and fixed some bugs mihad 8173d 20h /pci/tags/rel_WB_B3/sim/

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