OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [sim/] [rtl_sim/] [run/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5668d 01h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7695d 12h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
118 Some minor changes due to changes in core. tadejm 7695d 12h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7713d 15h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7719d 01h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
92 Update! mihad 7766d 07h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
81 Updated synchronization in top level fifo modules. mihad 7898d 11h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
73 Bug fixes, testcases added. mihad 7907d 17h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
72 *** empty log message *** mihad 7954d 21h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
63 Added additional testcase and changed rst name in BIST to trst mihad 8009d 23h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8020d 16h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8060d 00h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8068d 22h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
42 Removed out of date files mihad 8080d 23h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
26 Modified testbench and fixed some bugs mihad 8243d 17h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
22 Added short description for simulation running mihad 8261d 17h /pci/tags/rel_WB_B3/sim/rtl_sim/run/
17 *** empty log message *** mihad 8261d 19h /pci/tags/rel_WB_B3/sim/rtl_sim/run/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.