| Rev |
Log message |
Author |
Age |
Path |
| 154 |
New directory structure. |
root |
5574d 02h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 141 |
This commit was manufactured by cvs2svn to create tag 'wb2hpi'. |
|
7445d 22h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 140 |
Update! SPOCI Implemented! |
mihad |
7445d 22h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 137 |
def_wb_imagex_addr_map defined correctly |
fr2201 |
7473d 00h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 136 |
Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) |
fr2201 |
7473d 01h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 132 |
Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles. |
mihad |
7481d 23h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 131 |
Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly. |
mihad |
7485d 22h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 130 |
The wbs B3 to B2 translation logic had wrong reset wire connected! |
mihad |
7490d 22h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 128 |
Some warning cleanup. |
simons |
7492d 01h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 126 |
ifdef - endif statements put in separate lines for flint compatibility. |
simons |
7499d 18h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 124 |
Added missing signals to 2 sensitivity lists. Everything works the same as before. |
tadejm |
7538d 01h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 122 |
mbist signals updated according to newest convention |
markom |
7545d 01h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 117 |
WB Master is now WISHBONE B3 compatible. |
tadejm |
7601d 13h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 116 |
Corrected bug when writing to FIFO (now it is registered). |
tadejm |
7601d 13h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 115 |
Added signals for WB Master B3. |
tadejm |
7601d 14h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 113 |
ifdefs moved to thier own lines, this confuses some of the tools. |
simons |
7608d 16h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 111 |
synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. |
simons |
7608d 21h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 110 |
Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB. |
mihad |
7610d 20h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 108 |
Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. |
tadejm |
7614d 18h |
/pci/tags/wb2hpi/rtl/verilog/ |
| 106 |
Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet. |
mihad |
7619d 16h |
/pci/tags/wb2hpi/rtl/verilog/ |
