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[/] [pci/] [trunk/] - Rev 116

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Rev Log message Author Age Path
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7598d 16h /pci/trunk/
115 Added signals for WB Master B3. tadejm 7598d 16h /pci/trunk/
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7605d 19h /pci/trunk/
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7606d 00h /pci/trunk/
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.		 mihad 7607d 23h /pci/trunk/
109 There was missing path to hdl.var file. tadejm 7611d 20h /pci/trunk/
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7611d 20h /pci/trunk/
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7611d 20h /pci/trunk/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7616d 19h /pci/trunk/
105 Wrong pci_bridge32.v file included in the project! mihad 7622d 02h /pci/trunk/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7622d 04h /pci/trunk/
103 Added test application and modified files to support it. mihad 7669d 02h /pci/trunk/
102 Cleanup! mihad 7669d 02h /pci/trunk/
101 Added simulation files. mihad 7669d 02h /pci/trunk/
100 Cleanup! mihad 7669d 02h /pci/trunk/
99 Cleanup! mihad 7669d 02h /pci/trunk/
98 Cleanup. mihad 7669d 02h /pci/trunk/
97 Doing a little bit of cleanup. mihad 7669d 02h /pci/trunk/
96 Update! mihad 7669d 03h /pci/trunk/
95 Removed this file, because it was too large - long download time. mihad 7669d 03h /pci/trunk/

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