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[/] [pci/] [trunk/] [rtl/] [verilog/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5572d 19h /pci/trunk/rtl/verilog/
153 Write burst performance patch applied.
Not tested. Everything should be backwards
compatible, since functional code is ifdefed.		 mihad 6552d 14h /pci/trunk/rtl/verilog/
150 The control inputs from PCI are now muxed with control outputs
using output enable state for given signal.		 mihad 7201d 13h /pci/trunk/rtl/verilog/
149 Removed some unused signals. mihad 7236d 11h /pci/trunk/rtl/verilog/
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7236d 12h /pci/trunk/rtl/verilog/
147 Removed unsinthesizable !== comparation. mihad 7239d 18h /pci/trunk/rtl/verilog/
143 Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.		 mihad 7279d 14h /pci/trunk/rtl/verilog/
142 Single PCI Master write fix. mihad 7389d 10h /pci/trunk/rtl/verilog/
140 Update! SPOCI Implemented! mihad 7444d 15h /pci/trunk/rtl/verilog/
137 def_wb_imagex_addr_map defined correctly fr2201 7471d 17h /pci/trunk/rtl/verilog/
136 Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) fr2201 7471d 18h /pci/trunk/rtl/verilog/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7480d 16h /pci/trunk/rtl/verilog/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7484d 15h /pci/trunk/rtl/verilog/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7489d 15h /pci/trunk/rtl/verilog/
128 Some warning cleanup. simons 7490d 17h /pci/trunk/rtl/verilog/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7498d 11h /pci/trunk/rtl/verilog/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7536d 17h /pci/trunk/rtl/verilog/
122 mbist signals updated according to newest convention markom 7543d 18h /pci/trunk/rtl/verilog/
117 WB Master is now WISHBONE B3 compatible. tadejm 7600d 06h /pci/trunk/rtl/verilog/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7600d 06h /pci/trunk/rtl/verilog/

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