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[/] [pci/] [trunk/] [rtl/] [verilog/] - Rev 156

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Rev Log message Author Age Path
154 New directory structure. root 5613d 13h /pci/trunk/rtl/verilog/
153 Write burst performance patch applied.
Not tested. Everything should be backwards
compatible, since functional code is ifdefed.		 mihad 6593d 09h /pci/trunk/rtl/verilog/
150 The control inputs from PCI are now muxed with control outputs
using output enable state for given signal.		 mihad 7242d 08h /pci/trunk/rtl/verilog/
149 Removed some unused signals. mihad 7277d 06h /pci/trunk/rtl/verilog/
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7277d 06h /pci/trunk/rtl/verilog/
147 Removed unsinthesizable !== comparation. mihad 7280d 13h /pci/trunk/rtl/verilog/
143 Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines.
Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers.		 mihad 7320d 09h /pci/trunk/rtl/verilog/
142 Single PCI Master write fix. mihad 7430d 05h /pci/trunk/rtl/verilog/
140 Update! SPOCI Implemented! mihad 7485d 10h /pci/trunk/rtl/verilog/
137 def_wb_imagex_addr_map defined correctly fr2201 7512d 12h /pci/trunk/rtl/verilog/
136 Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) fr2201 7512d 12h /pci/trunk/rtl/verilog/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7521d 11h /pci/trunk/rtl/verilog/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7525d 09h /pci/trunk/rtl/verilog/
130 The wbs B3 to B2 translation logic had wrong reset wire connected! mihad 7530d 10h /pci/trunk/rtl/verilog/
128 Some warning cleanup. simons 7531d 12h /pci/trunk/rtl/verilog/
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7539d 05h /pci/trunk/rtl/verilog/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7577d 12h /pci/trunk/rtl/verilog/
122 mbist signals updated according to newest convention markom 7584d 13h /pci/trunk/rtl/verilog/
117 WB Master is now WISHBONE B3 compatible. tadejm 7641d 01h /pci/trunk/rtl/verilog/
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7641d 01h /pci/trunk/rtl/verilog/

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