OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [trunk/] [sim/] - Rev 154

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5567d 22h /pci/trunk/sim/
152 Some regression tests were failing during completion expired testing. mihad 7003d 15h /trunk/sim/
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.		 mihad 7231d 15h /trunk/sim/
140 Update! SPOCI Implemented! mihad 7439d 18h /trunk/sim/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.		 mihad 7475d 19h /trunk/sim/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.		 mihad 7479d 18h /trunk/sim/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7531d 20h /trunk/sim/
118 Some minor changes due to changes in core. tadejm 7595d 09h /trunk/sim/
109 There was missing path to hdl.var file. tadejm 7608d 13h /trunk/sim/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7613d 12h /trunk/sim/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7618d 22h /trunk/sim/
95 Removed this file, because it was too large - long download time. mihad 7665d 20h /trunk/sim/
92 Update! mihad 7666d 04h /trunk/sim/
81 Updated synchronization in top level fifo modules. mihad 7798d 08h /trunk/sim/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7801d 13h /trunk/sim/
73 Bug fixes, testcases added. mihad 7807d 14h /trunk/sim/
72 *** empty log message *** mihad 7854d 18h /trunk/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7909d 20h /trunk/sim/
62 Added BIST signals for RAMs. mihad 7912d 13h /trunk/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7920d 13h /trunk/sim/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.