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[/] [pci/] [trunk/] [sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5570d 18h /pci/trunk/sim/
152 Some regression tests were failing during completion expired testing. mihad 7006d 12h /trunk/sim/
148 Changed minimum pci image size to 256 bytes because
of some PC system problems with size of IO images.
mihad 7234d 11h /trunk/sim/
140 Update! SPOCI Implemented! mihad 7442d 15h /trunk/sim/
132 Compact PCI Hot Swap support added.
New testcases added.
Specification updated.
Test application changed to support WB B3 cycles.
mihad 7478d 16h /trunk/sim/
131 Moved top.v to bench directory. Removed unneeded meta_flop,
modified files list files accordingly.
mihad 7482d 14h /trunk/sim/
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7534d 17h /trunk/sim/
118 Some minor changes due to changes in core. tadejm 7598d 06h /trunk/sim/
109 There was missing path to hdl.var file. tadejm 7611d 10h /trunk/sim/
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7616d 09h /trunk/sim/
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7621d 18h /trunk/sim/
95 Removed this file, because it was too large - long download time. mihad 7668d 16h /trunk/sim/
92 Update! mihad 7669d 00h /trunk/sim/
81 Updated synchronization in top level fifo modules. mihad 7801d 05h /trunk/sim/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7804d 10h /trunk/sim/
73 Bug fixes, testcases added. mihad 7810d 11h /trunk/sim/
72 *** empty log message *** mihad 7857d 14h /trunk/sim/
63 Added additional testcase and changed rst name in BIST to trst mihad 7912d 17h /trunk/sim/
62 Added BIST signals for RAMs. mihad 7915d 09h /trunk/sim/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7923d 09h /trunk/sim/

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