URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

Subversion Repositories pcie_ds_dma

[/] [pcie_ds_dma/] - Rev 35

Rev	Log message	Author	Age	Path
35	Add unistd.h for close() syscall.	v.karak	4036d 12h	/pcie_ds_dma/
34	Remove __devinit and __devexit prefixes.	v.karak	4036d 13h	/pcie_ds_dma/
33	Correctly search PCI Express Capability Register Set.	v.karak	4036d 13h	/pcie_ds_dma/
32	Set 125 MHz for wishbone bus. Data transfered from TEST_GEN to computer without errors.	dsmv	4040d 21h	/pcie_ds_dma/
31	correct wb_test	dsmv	4040d 21h	/pcie_ds_dma/
30	data read from wb_gen with error	dsmv	4048d 01h	/pcie_ds_dma/
29	Correct dmar, rst for wb_test; Add STATUS register.	dsmv	4048d 01h	/pcie_ds_dma/
28	add test_dio.cfg out_dio.cfg	dsmv	4059d 20h	/pcie_ds_dma/
27	update adm_test	dsmv	4059d 20h	/pcie_ds_dma/
26	update for adm_test	dsmv	4059d 20h	/pcie_ds_dma/
25	update test_main.cfg	dsmv	4077d 23h	/pcie_ds_dma/
24	update test_main.cfg	dsmv	4077d 23h	/pcie_ds_dma/
23	Correct default settings value.	v.karak	4078d 04h	/pcie_ds_dma/
22	correct wishbone_test_en.htm	dsmv	4090d 02h	/pcie_ds_dma/
21	debug ambpex5_sx50t_wishbone	dsmv	4090d 02h	/pcie_ds_dma/
20	debug wb_test	dsmv	4090d 02h	/pcie_ds_dma/
19		dsmv	4090d 03h	/pcie_ds_dma/
18	read block_id - ok	dsmv	4090d 19h	/pcie_ds_dma/
17	ambpex5_sx50t_wishbone - simulation is ok	dsmv	4111d 22h	/pcie_ds_dma/
16	ambpex5_sx50t_wishbone - add files, don't work	dsmv	4112d 20h	/pcie_ds_dma/