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URL https://opencores.org/ocsvn/pcie_ds_dma/pcie_ds_dma/trunk

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[/] [pcie_ds_dma/] [trunk/] - Rev 34

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Rev Log message Author Age Path
34 Remove __devinit and __devexit prefixes. v.karak 3990d 20h /pcie_ds_dma/trunk/
33 Correctly search PCI Express Capability Register Set. v.karak 3990d 20h /pcie_ds_dma/trunk/
32 Set 125 MHz for wishbone bus. Data transfered from TEST_GEN to computer without errors. dsmv 3995d 05h /pcie_ds_dma/trunk/
31 correct wb_test dsmv 3995d 05h /pcie_ds_dma/trunk/
30 data read from wb_gen with error dsmv 4002d 08h /pcie_ds_dma/trunk/
29 Correct dmar, rst for wb_test; Add STATUS register. dsmv 4002d 08h /pcie_ds_dma/trunk/
28 add test_dio.cfg out_dio.cfg dsmv 4014d 04h /pcie_ds_dma/trunk/
27 update adm_test dsmv 4014d 04h /pcie_ds_dma/trunk/
26 update for adm_test dsmv 4014d 04h /pcie_ds_dma/trunk/
25 update test_main.cfg dsmv 4032d 06h /pcie_ds_dma/trunk/
24 update test_main.cfg dsmv 4032d 06h /pcie_ds_dma/trunk/
23 Correct default settings value. v.karak 4032d 12h /pcie_ds_dma/trunk/
22 correct wishbone_test_en.htm dsmv 4044d 09h /pcie_ds_dma/trunk/
21 debug ambpex5_sx50t_wishbone dsmv 4044d 10h /pcie_ds_dma/trunk/
20 debug wb_test dsmv 4044d 10h /pcie_ds_dma/trunk/
19 dsmv 4044d 10h /pcie_ds_dma/trunk/
18 read block_id - ok dsmv 4045d 03h /pcie_ds_dma/trunk/
17 ambpex5_sx50t_wishbone - simulation is ok dsmv 4066d 05h /pcie_ds_dma/trunk/
16 ambpex5_sx50t_wishbone - add files, don't work dsmv 4067d 04h /pcie_ds_dma/trunk/
15 Add ambpex5_sx50t_wishbone\src dsmv 4067d 05h /pcie_ds_dma/trunk/

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