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Rev Log message Author Age Path
16 Added master error counter variable, added simulation timout limit rehayes 5353d 06h /pit/
15 Fix blocking assigment rehayes 5381d 06h /pit/
14 Cosmetic update, changed no-blocking assigment to blocking assigment rehayes 5450d 04h /pit/
13 Update to rev 0.3, added SINGLE_CYCLE parameter rehayes 5480d 08h /pit/
12 Fixed for single cycle reads rehayes 5481d 03h /pit/
11 Changed read task to capture data at rising edge of clock rehayes 5481d 03h /pit/
10 Added SINGLE_CYCLE parameter for WISHBONE bus cycles rehayes 5482d 06h /pit/
9 fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice. rehayes 5487d 23h /pit/
8 Fix ack signal in testbench rehayes 5488d 00h /pit/
7 Reflection of minor corrections rehayes 5492d 06h /pit/
6 Reflection of minor corrections rehayes 5492d 06h /pit/
5 rehayes 5530d 02h /pit/
4 Initial Release March 14, 2009 - Bob Hayes rehayes 5530d 02h /pit/
3 Initial Release March 14, 2009 - Bob Hayes rehayes 5530d 02h /pit/
2 Initial Release March 14, 2009 - Bob Hayes rehayes 5530d 02h /pit/
1 The project was created and the structure was created root 5530d 17h /pit/

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