URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] - Rev 17

Rev	Log message	Author	Age	Path
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5399d 19h	/pit/
16	Added master error counter variable, added simulation timout limit	rehayes	5510d 21h	/pit/
15	Fix blocking assigment	rehayes	5538d 22h	/pit/
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5607d 20h	/pit/
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5637d 23h	/pit/
12	Fixed for single cycle reads	rehayes	5638d 19h	/pit/
11	Changed read task to capture data at rising edge of clock	rehayes	5638d 19h	/pit/
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5639d 22h	/pit/
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5645d 15h	/pit/
8	Fix ack signal in testbench	rehayes	5645d 16h	/pit/
7	Reflection of minor corrections	rehayes	5649d 21h	/pit/
6	Reflection of minor corrections	rehayes	5649d 21h	/pit/
5		rehayes	5687d 17h	/pit/
4	Initial Release March 14, 2009 - Bob Hayes	rehayes	5687d 18h	/pit/
3	Initial Release March 14, 2009 - Bob Hayes	rehayes	5687d 18h	/pit/
2	Initial Release March 14, 2009 - Bob Hayes	rehayes	5687d 18h	/pit/
1	The project was created and the structure was created	root	5688d 09h	/pit/